FPGA Verilog HDL
FPGA 순차 논리 회로
Program Counter
2021. 5. 23. 22:50
사용 툴 : Xilinx Vivado
언어 : Verilog HDL
보드 : Zybo z7-20
SR 래치(SR Latch)
module SR_latch(
input S,
input R,
output Q,
output Qbar
);
nor (Q, R, Qbar);
nor (Qbar, S, Q);
endmodule
D 래치(D Latch)
module D_latch(
input D, E,
output Q, Qbar
);
wire Dbar, S, R;
not (Dbar, D);
and (R, E, Dbar);
and (S, E, D);
SR_latch G (.S(S), .R(R), .Q(Q), .Qbar(Qbar));
endmodule
D 플립플롭(D Flip Flop)
module D_flip_flop(
input D, reset, preset,
input clk,
output reg Q,
output reg Qbar
);
wire Dbar;
not (Dbar, D);
always @(posedge clk or negedge reset or negedge preset)begin
if (!reset | !preset) begin
case ({reset, preset})
2'b01: begin Q = 0; Qbar = 1; end
2'b10: begin Q = 1; Qbar = 0; end
endcase
end
else begin
Q <= D;
Qbar <= Dbar;
end
end
endmodule
JK 플립플롭(JK Flip Flop)
module JK_flip_flop(
input K,
input J,
input preset,
input reset,
input clk,
output reg Q,
output reg Qbar
);
always @(posedge clk or negedge preset or negedge reset) begin
if (reset && preset) begin
case({J, K})
2'b00: begin Q <= Q; Qbar <= Qbar; end
2'b01: begin Q <= 0; Qbar <= 1; end
2'b10: begin Q <= 1; Qbar <= 0; end
//2'b11: begin Q <= Qbar; Qbar <= Q; end
2'b11: begin Q <= ~Q; Qbar <= !Qbar; end
endcase
end
case({reset, preset})
2'b01: begin Q <= 0; Qbar <= 1; end
2'b10: begin Q <= 1; Qbar <= 0; end
endcase
end
endmodule
T 플립플롭(T Flip Flop)
module T_flip_flop_negedge(
input T,
input clk,
input preset,
input reset,
output reg Q
);
always @(negedge clk or negedge preset or negedge reset) begin
if (!reset | !preset) begin
case ({reset, preset})
2'b01 : Q = 0;
2'b10 : Q = 1;
endcase
end
else begin
if(T) Q = ~Q;
else Q = Q;
end
end
endmodule
시프트 레지스터 SIPO(Shift Register Serial Input Parallel Output)
module shift_register_SIPO(
input D,
input clk, E, reset, preset,
output [3:0] Q
);
// 구조적 모델링
// wire clk_in;
// and (clk_in, clk, E);
// D_flip_flop Q3 (.D(D), .Q(Q[3]), .clk(clk_in), .reset(reset), .preset(preset));
// D_flip_flop Q2 (.D(Q[3]), .Q(Q[2]), .clk(clk_in), .reset(reset), .preset(preset));
// D_flip_flop Q1 (.D(Q[2]), .Q(Q[1]), .clk(clk_in), .reset(reset), .preset(preset));
// D_flip_flop Q0 (.D(Q[1]), .Q(Q[0]), .clk(clk_in), .reset(reset), .preset(preset));
// 동작적 모델링
reg [3:0] temp;
always @(posedge clk or negedge reset or negedge preset) begin
case ({reset, preset})
2'b01: temp <= 4'b0000;
2'b10: temp <= 4'b1111;
endcase
// if (E && reset && preset) begin
// temp = temp >> 1;
// temp[3] <= D;
// end
if (E && reset && preset) begin
temp = temp << 1;
temp[0] <= D;
end
end
시프트 레지스터 PISO(Shift Register Parallel Input Serial Output)
module shift_register_PISO(
input [3:0] D,
input clk,
input load,
input reset, preset,
output Q
);
// 구조적 모델링
// wire load_bar, Q3, Q2, Q1, clk_in;
// wire [3:0] Din;
// wire load_bar, Q3, Q2, Q1;
// wire [2:0] shift, data, Din;
// not (load_bar, load);
// and (clk_in, clk, load);
// nand (Din[3], load_bar, D[3]);
// nand (Din[2], load_bar, D[2]);
// nand (Din[1], load_bar, D[1]);
// nand (Din[0], load_bar, D[0]);
// not (load_bar, load);
// and (shift[2], load, Q3);
// and (shift[1], load, Q2);
// and (shift[0], load, Q1);
// and (data[2], load_bar, D[2]);
// and (data[1], load_bar, D[1]);
// and (data[0], load_bar, D[0]);
// or (Din[2], shift[2], data[2]);
// or (Din[1], shift[1], data[1]);
// or (Din[0], shift[0], data[0]);
// D_flip_flop G3 (.D(1'b0), .clk(clk_in), .preset(Din[3]), .Q(Q3), .reset(1'b1));
// D_flip_flop G2 (.D(Q3), .clk(clk_in), .preset(Din[2]), .Q(Q2), .reset(1'b1));
// D_flip_flop G1 (.D(Q2), .clk(clk_in), .preset(Din[1]), .Q(Q1), .reset(1'b1));
// D_flip_flop G0 (.D(Q1), .clk(clk_in), .preset(Din[0]), .Q(Q), .reset(1'b1));
// D_flip_flop G3 (.D(D[3]), .clk(clk), .preset(preset), .reset(reset), .Q(Q3));
// D_flip_flop G2 (.D(Din[2]), .clk(clk), .preset(preset), .reset(reset), .Q(Q2));
// D_flip_flop G1 (.D(Din[1]), .clk(clk), .preset(preset), .reset(reset), .Q(Q1));
// D_flip_flop G0 (.D(Din[0]), .clk(clk), .preset(preset), .reset(reset), .Q(Q));
reg [3:0] temp;
always @(posedge clk) begin
if (load) begin
temp <= temp >> 1;
end
else begin
if (reset && preset)
temp <= D;
end
end
assign Q = temp[0];
always @(posedge clk or negedge reset or negedge preset) begin
case ({reset, preset})
2'b01: temp = 4'b0000;
2'b10: temp = 4'b1111;
endcase
end
endmodule
카운터(Counter)
module counter_asy_up(
input clk,
output [3:0] C
);
reg [3:0] counter;
initial counter = 0;
always @(negedge clk) begin
counter = counter + 1;
end
assign C = counter;
endmodule
module counter_asy_down(
input T,
input clk,
input reset,
input preset,
output [3:0] C
);
T_flip_flop G0 (.T(T), .clk(clk), .reset(reset), .preset(preset), .Q(C[0]));
T_flip_flop G1 (.T(T), .clk(C[0]), .reset(reset), .preset(preset), .Q(C[1]));
T_flip_flop G2 (.T(T), .clk(C[1]), .reset(reset), .preset(preset), .Q(C[2]));
T_flip_flop G3 (.T(T), .clk(C[2]), .reset(reset), .preset(preset), .Q(C[3]));
endmodule
module counter_BCD_up(
input T,
input clk,
input reset,
input preset,
output [3:0] C
);
wire T2, T3, reset10, reset_in;
and(T2, C[0], C[1]);
and(T3, T2, C[2]);
nand(reset10, C[3], C[1]);
and (reset_in, reset, reset10);
T_flip_flop_negedge G0 (.T(T), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[0]));
T_flip_flop_negedge G1 (.T(C[0]), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[1]));
T_flip_flop_negedge G2 (.T(T2), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[2]));
T_flip_flop_negedge G3 (.T(T3), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[3]));
endmodule
module counter_syn_up(
input T,
input clk,
input reset,
input preset,
output [3:0] C
);
wire T2, T3;
and(T2, C[0], C[1]);
and(T3, T2, C[2]);
T_flip_flop_negedge G0 (.T(T), .clk(clk), .reset(reset), .preset(preset), .Q(C[0]));
T_flip_flop_negedge G1 (.T(C[0]), .clk(clk), .reset(reset), .preset(preset), .Q(C[1]));
T_flip_flop_negedge G2 (.T(T2), .clk(clk), .reset(reset), .preset(preset), .Q(C[2]));
T_flip_flop_negedge G3 (.T(T3), .clk(clk), .reset(reset), .preset(preset), .Q(C[3]));
endmodule
분주기(Prescaler)
module clk_divider_10(
input T,
input clk,
input reset,
input preset,
output Q
);
wire T2, T3, reset10, reset_in;
wire [2:0] C;
and(T2, C[0], C[1]);
and(T3, T2, C[2]);
nand(reset10, Q, C[1]);
and (reset_in, reset, reset10);
T_flip_flop_negedge G0 (.T(T), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[0]));
T_flip_flop_negedge G1 (.T(C[0]), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[1]));
T_flip_flop_negedge G2 (.T(T2), .clk(clk), .reset(reset_in), .preset(preset), .Q(C[2]));
T_flip_flop_negedge G3 (.T(T3), .clk(clk), .reset(reset_in), .preset(preset), .Q(Q));
endmodule
module clk_divder_16(
input T,
input clk,
input reset,
input preset,
output Q
);
wire T2, T3;
wire [2:0] C;
and(T2, C[0], C[1]);
and(T3, T2, C[2]);
T_flip_flop_negedge G0 (.T(T), .clk(clk), .reset(reset), .preset(preset), .Q(C[0]));
T_flip_flop_negedge G1 (.T(C[0]), .clk(clk), .reset(reset), .preset(preset), .Q(C[1]));
T_flip_flop_negedge G2 (.T(T2), .clk(clk), .reset(reset), .preset(preset), .Q(C[2]));
T_flip_flop_negedge G3 (.T(T3), .clk(clk), .reset(reset), .preset(preset), .Q(Q));
endmodule