FPGA 조합 논리 회로

사용 툴 : Xilinx Vivado

언어 : Verilog HDL

보드 : Zybo z7-20

 

반가산기(Half Adder)

module half_adder(
    input X,
    input Y,
    output S,
    output C
    );
    
    xor (S, X, Y);
    and (C, X, Y);
endmodule

 

전가산기(Full Adder)

module full_adder(
    input x,
    input y,
    input cin,
    output s,
    output cout
    );
    
    wire ws, wc0, wc1;
    
    half_adder G1 (.X(x), .Y(y), .S(ws), .C(wc0));
    half_adder G2 (.X(ws), .Y(cin), .S(s), .C(wc1));
    or (cout, wc0, wc1);
    
endmodule

 

1비트 비교기(1bit Comparator)

module Comparator(
    input x,
    input y,
    output equal,
    output not_equal,
    output bigger,
    output less
    );
    
    wire xbar, ybar;
    
    not (xbar, x);
    not (ybar, y);
    xor (not_equal, x, y);
    not (equal, not_equal);
    and (bigger, x, ybar);
    and (less, xbar, y);
    
endmodule

 

2비트 비교기(2bit Comparator)

module comparator_2bit(
    input [1:0] x,
    input [1:0] y,
    output reg equal,
    output reg not_equal,
    output reg bigger,
    output reg less
    );
    
    always @(x or y) begin
        if (x == y) begin
            equal = 1;
            not_equal = 0;
            bigger = 0;
            less = 0;
        end
        else if (x > y) begin
            equal = 0;
            not_equal = 1;
            bigger = 1;
            less = 0;
        end
        else if (x < y) begin
            equal = 0;
            not_equal = 1;
            bigger = 0;
            less = 1;
        end
    end
    
endmodule

 

8-3 인코더(Encoder)

module encoder_8_3(
    input [7:0] signal,
    output [2:0] code
    );
    
    or (code[0], signal[1], signal[3], signal[5], signal[7]);
    or (code[1], signal[2], signal[3], signal[6], signal[7]);
    or (code[2], signal[4], signal[5], signal[6], signal[7]);
    
endmodule

 

3-8 디코더(Decoder)

module decoder_3_8(
    input [2:0] code,
    output [7:0] signal
    );
    
    wire [2:0] code_bar;
    
    not (code_bar[0], code[0]);
    not (code_bar[1], code[1]);
    not (code_bar[2], code[2]);
    
    and (signal[0], code_bar[0], code_bar[1], code_bar[2]);
    and (signal[1], code[0], code_bar[1], code_bar[2]);
    and (signal[2], code_bar[0], code[1], code_bar[2]);
    and (signal[3], code[0], code[1], code_bar[2]);
    and (signal[4], code_bar[0], code_bar[1], code[2]);
    and (signal[5], code[0], code_bar[1], code[2]);
    and (signal[6], code_bar[0], code[1], code[2]);
    and (signal[7], code[0], code[1], code[2]);

endmodule

 

8-1 멀티플렉서(Multiplexer)

module multiplexer_8_1(
    input [7:0] D,
    input [2:0] S,
    output Q
    );
    
    wire [2:0] Sbar;
    wire [7:0] w;
    
    not (Sbar[0], S[0]);
    not (Sbar[1], S[1]);
    not (Sbar[2], S[2]);
    
    and (w[0], D[0], Sbar[0], Sbar[1], Sbar[2]);
    and (w[1], D[1], S[0], Sbar[1], Sbar[2]);
    and (w[2], D[2], Sbar[0], S[1], Sbar[2]);
    and (w[3], D[3], S[0], S[1], Sbar[2]);
    and (w[4], D[4], Sbar[0], Sbar[1], S[2]);
    and (w[5], D[5], S[0], Sbar[1], S[2]);
    and (w[6], D[6], Sbar[0], S[1], S[2]);
    and (w[7], D[7], S[0], S[1], S[2]);
    
    or (Q, w[0], w[1], w[2], w[3], w[4], w[5], w[6], w[7]);
    
endmodule

 

1-8 디멀티플렉서(Demultiplexer)

module demultiplexer_1_8(
    input D,
    input [2:0] S,
    output [7:0] Q
    );
    
    wire [2:0] Sbar;
    
    not (Sbar[0], S[0]);
    not (Sbar[1], S[1]);
    not (Sbar[2], S[2]);
    
    and (Q[0], D, Sbar[0], Sbar[1], Sbar[2]);
    and (Q[1], D, S[0], Sbar[1], Sbar[2]);
    and (Q[2], D, Sbar[0], S[1], Sbar[2]);
    and (Q[3], D, S[0], S[1], Sbar[2]);
    and (Q[4], D, Sbar[0], Sbar[1], S[2]);
    and (Q[5], D, S[0], Sbar[1], S[2]);
    and (Q[6], D, Sbar[0], S[1], S[2]);
    and (Q[7], D, S[0], S[1], S[2]);
    
endmodule